1. Field of the Invention
The present invention relates to a test apparatus and a test method. More particularly, the present invention relates to a test apparatus and a test method for detecting a delay failure of a circuit.
2. Description of the Related Art
In connection with miniaturization of LSI in recent years, miniaturization of logical elements in the LSI is progressing. Accordingly, driving performance of the logic element decreases, and thus a delay failure of the logic element becomes a major cause for a failure of the LSI.
The following documents relate to a scan test for detecting this kind of delay failure and discloses a scan method which switches a test pattern of a cycle to a test pattern of its next cycle at a high speed (cf. J. P. Hurst, N. Kanopoulos, “Flip-Flop Sharing in Standard Scan Path to Enhance Delay Fault Testing of Sequential Circuits,” Asian Test Symposium 1995, IEEE, Nov. 23, 1995, p. 346–352; K. Hatayama, M. Ikeda, M. Takakura, S. Uchiyama, Y. Sakamoto, “Application of a Design for Delay Testability Approach to High Speed Logic LSIs,” Asian Test Symposium 1997, IEEE, Nov. 17, 1997, p. 112–115; N. A. Touba, E. J. McCluskey, “Applying Two-Pattern Tests Using Scan-Mapping,” IEEE VLSI Test Symposium 1996, IEEE, Apr. 28, 1996, p. 393–397; Eric MacDonald, N. A. Touba, “Delay Testing of SOI Circuits: Challenges with the History Effect,” International Test Conference 1999, IEEE, Sep. 27, 1999, p. 269–275. According to the documents, it is possible to detect whether or not a circuit operates within a predetermined delay time by controlling clock intervals of adjacent clocks (double clocks) and testing whether or not the circuit correctly operates.
According to the above tests using the double clocks, the absolute value of a delay time of a circuit is measured and acceptability of an LSI is determined based on the measured absolute value. Therefore, it is impossible to determine whether the measured delay is caused by the variance of a process or by a delay failure of a logic element.
Therefore, it is an object of the present invention to provide a test apparatus and a test method, which are capable of overcoming the above drawbacks. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.